VHDL or Verilog?

Re:VHDL or Verilog? by mzakharo1 on Monday May 01, 2017 @11:15AM (#14238152)

Little known in the industry, VHDL struct syntax allows for very neat and concise method to be used, called [Gaisler's method](http://www.gaisler.com/doc/vhdl2proc.pdf). The entire Processor and architecture is written using it (http://www.gaisler.com/index.php/downloads/leongrlib) - and it is fantastic to work with - it feels like a piece of object oriented programming, while using low level language of VHDL. Not sure if anyone has tried to apply Gasler's method to SystemVerilog, but verilog on its own falls quite short in this regard.

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Re:VHDL or Verilog? by krapht on Monday May 01, 2017 @02:10PM (#14239948)

Was Gaisler the first to write about it? I actually first heard about it from Mike Treseler, who is mentioned in this Powerpoint (http://ens.ewi.tudelft.nl/Education/courses/et4351/structure...)

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Re:VHDL or Verilog? by rektide on Monday May 01, 2017 @04:41PM (#14241348)

Slide 22 of this powerponit, Mike explicitly calls it Gaisler's Method. The term he uses "Structured VHDL" comes next slide.

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