If you can't produce reliable SRAM at 10nm no problem, if you want to integrate FPGAs that are build using a different process no problem, you want to scale up the same basic core design of 4 core clusters again just make the same small dies and interpose them based on market demands. This will allow Intel to sell Xeon SoCs/CPU's with 128 to 256 core which isn't viable if you put them all on the same die, it also means that they don't have to disable cores for different SKU's now if they want to make a 10 core CPU they just put 10 cores and not 12 with 2 of them disabled.
People also overlook the cost of the masks, a set of master masks cost a lot of money even their copies cost a small fortune and as we go into more and more intensive processes as far as radiation goes the lifespan of these masks shrinks in an ever increasing pace.
It sounds like a move from "Do we assume the next node will be ready for our most important chip in X years?" to "What parts of chips is the next node currently ready for?"
Fabbing smaller dies on lower-yield, leading edge processes would also be nice. Curious what the trade-offs will look like in terms of power/thermal vs a monolithic die design.
It also might mean large-core chips could be available sooner on new manufacturing processes (which tend to have a high failure rate until they're thoroughly debugged).
The difference between Sky Lake Celeron and Kaby Lake Celeron is small, but it's not like it's a big difference for i7 either. I don't think a lot of people are tossing out their Sky Lake CPUs and putting in Kaby Lake at any part of the performance curve; it's just if you're upgrading from something older (maybe Sandy or Ivy Bridge) or buying something new that you may want to go with the newer core design. Eg: Celeron G3920 (Skylake) vs G3930 (Kaby Lake) are both 2.9Ghz but G3930 is about $10 cheaper and may have a slightly nicer GPU.
Also, it allows Intel to increase the rate of innovation - for example by specifying how each silicon die(memory, interconnect, rf?, acceleration, etc) connects to the EMIB, and letting internal and maybe external groups work independently and maybe compete on better modules.
Shame this would be wasted on someone as close as Intel though.
No more IGP for high end Desktop CPU. Can easily mix and match CPU / GPU or even FPGA according to customer's requirement. I wonder why will this be on the market.
Another Point is Data Center First for new node. Why? What push them to make this decision? They literally have 95% market shares with healthy margin.
This can be very interesting especially if this can be expanded to other products. TSVs increase the pricing of certain products by a substantial margin and have pretty high failure rates, they also increase the internal resistance of components and can cause thermal issues.
HBM and 3Dxpoint built on EMIB can reduce the price of these components substantially, it can also make it viable again to split the dies of the IGP and the CPU allowing Intel have SKUs with different IGP configuration including EDRAM/SRAM without having to have multiple die designs.