klhugo

That is a very, very good point. I have no counter arguments. Thanks for sharing!

Truth is I don't have time to dig in this right now. I thought if the idea was good maybe I could motivate somebody else.

I just hope we can get rid of PoW the way it is soon.

Hell yeah, why do you think I'm getting married? :P As long as there is mutual support, I'd not worry. I'd be proud to be supported by my future wife.

For proof of work to be fair, you need a robust & secure job that produces results with a uniform distribution of zeros and ones. FHE gives you that, while performing useful computation.

> Hey @VitalikButerin, instead of doing proof of work with useless puzzles, why don't we use that massive GPU compute power to help science with numerical computation? We could wrap the problem using @HomomorphicEnc techniques. Efficiency would improve overtime. ASICs are welcome.

What's your opinion?

What about cosmic crisp?

I hope somebody at Microsoft read this. It goes far beyond security vulnerabilities. The Teams Linux client is barely usable. Chromebooks don't even have a client.

Could Microsoft expose an API and allow third party clients to be developed?

If your .vimrc is minimal, you will have a pretty good time using systems that implement "vim like" text editing. Take Overleaf for example, no vimrc is available, but I'm quite happy with what I got, and sometimes I even forget I'm in the browser.

And fast! I got easily 3 orders of magnitude speedup. I used to load CSVs with pandas and do typical filtering operations... oh boy, some of the stuff would take a hole morning, not to mention the memory usage. I do all that in minutes now.

Here is the thing made me a happier person this year: I realized when CSVs take too long to load, I should not be using them in the first place!

I love SQLite now <3

I'm in the middle of a PhD myself, so take my opinion with a grain of salt.

I actually agree with the author, certain fields are just very complex to develop a solid understand without proper mentoring and support you would get as a grad student.

That said, maybe the real issue is not the fact we need two PhDs each, but the question I want to raise, do PhDs need to take 4/5/6 years? (I'm not even considering the cases where people, like myself, do a 2 year master program before the PhD...). Honestly, in my humble opinion, it is not necessary.

Maybe universities could develop "industry focused dual PhD programs" to target specifically crazy folks like us :)

This might be something worth to fight for.

Quick comment, not an expert, but environ vars keep their state after the program is called. From a functional programming perspective, or just for my own sanity, wouldn’t it be more interesting to keep the states into minimum?

Absolutely not. "Apple Silicon" is branding for their own processor. This is a road to an opensource ecosystem in HW design.

Design is not all. There is a reason IC design houses are vanishing, it is too expensive to design custom chips. Only large companies can afford the tapeouts, testing, Packaging, and large volume production.

Using fancy features does not make you a better programmer. It is the other way around.

Misleading title, change it, it just spreads panic.

That was a very nice breakdown of costs for a side project. Thanks for sharing this!

During a CC certification, the design-house, mask shop, and fab are certified to reduce the chances of the chip being tampered. The certification ensures that all those places have decent security practices and protocols. It helps but is quite far from completely mitigating it.

I don't have any reference of a mask being modified to give to you, but it is so easy to do it that we don't actually need evidences to be worried.

If you think about it, just by changing implantation parameters on the transistors that form a ring oscillator for generating random numbers can bias it (this does not require not even modifying the mask).

Yep. Great times are coming :D

I think if you can enforce that the user will resynthesize the design on his own, and you make sure the synthesis/placement is different, you are way ahead of any other AISC alternative in terms of trust.

A couple things:

   1. FPGAs are easier to verify cause they are regular structures.
   2. How do you insert a backdoor in an FPGA at the supply chain if you don't know what is the exact logic that is going to be uploaded?

It was just a simple example. There are counter-measures WAY more complex than a simple two lead sensor. I was part of a CC certified chip design, and I can tell you we must implement tests for every single countermeasure in the chip. But still you have no means to check whether your sensor/countermeasure hasn't been tampered all together in the supply chain.

You are right, but in the scope of chip design we can solve all that. What we can not solve is supply chain trust (how do you now your temp sensor has not been tampered?)

Excellent work. I completely agree that today the easiest option to develop safe hardware is using FPGAs.

Two things to look forward:

   1. Usage of open source FPGA synthesis and implementation tools
   2. Usage of open source FPGA chips :)

I've already seen some traction happening for open source FPGA tools, but open source FPGA chips are only in my head (as far as I know).

I'm a chip designer myself, and for years I have been thinking on kickstarting something to pay for a tapeout of an open source FPGA. If anyone is interested let me know, I live in Ontario/Canada.

I have to agree with you.

What impresses me even more is that they are selling it already, and marketing as “open-source”. I would leave a note here that if anybody is interested in doing something similar, please get some feedback from community before starting commercialization.

Also, you guys should definitely do some research about side-channel attacks. I quickly inspect the source code and did not find any counter-measure.

This article would be better represented with the title “Open Source Logic”, since it basically refers to the adoption of FPGAs on the cloud. IMHO Open Source Silicon refers to the physical design and process information for actual manufacturing of a chip.

That said, I do believe significant improvements are being achieved to lower the barrier for HW development. One thing that is not often mentioned is that even for experienced hardware developers (like myself) it is very hard/time consuming to fully implement the full stack of technologies required to accelerate computation on a PCI express connected FPGA board.

I haven’t followed recent trend of HLS, thus I can certainly say that with the traditional approach verilog/SV, it would be only a handful of people that could actually make use of those FPGAs.

A lot is due to bots.

I stoped mainly because I need to work on my PhD. But the code there was very solid on my tests. I hope I can get back at it early next year :)