Good points. But it should be mentioned that, once you have your logic working in an FPGA, the additional step to make it ready for silicon is comparatively small. So I don't think it's too bad to confound the two.

The ASIC flow is way more involved than the FPGA flow, you need to think about all sorts of other things, like what pads you want on your chip, how you are going to generate clocks, floor planning, power distribution, test, and a whole raft of other issues. Going from RTL to GDS2 for even a simple chip would take 3 months work as an absolute minimum (and that's just to get it ready to send to the fab. You then have a whole lot of work when it comes back (you need to have boards designed for testing the chip).

While this is true, this work is typically done by a different person than the one designing the RTL, and it takes 1-2 month at most if there are minimal changes to the overall physical design. We are able to iterate on designs at a rate of ~6 month with a team of ~10 people.

No. It's many, many months of work.

The physical design in an fpga solution is pretty much done for you. You've also got a nice package (power, warpage, SI all done). In an ASIC you start this enormous task from scratch. You've also got to implement (and interface with) a huge amount of test, which again, is mostly done for you when you purchase your working FPGA.

Not to mention the fact that there's little margin for error with an ASIC, there's no second chance to try again without spending a load of money. So the test and verification of your circuits is much higher. (I know your said "working" design but there is no such design that is guaranteed to work when changed).

I do both FPGA and high performance ASIC design for a living - there is typically a pretty big gap between something designed well for an FPGA and something designed well for an ASIC. You’re probably making use of FPGA-specific hard IP (memories, PLLs, PHYs, etc.) that you’ll need to replace, and the logic will have been implemented in a way that’s tuned to the timing trade offs on an FPGA. Clicking “recompile” is only the case if your design has terrible performance in an FPGA and you want awful performance in an ASIC too.

That is not true. The synthesis and layout have to be done separately for the ASIC. That is a more time consuming process than writing verilog code.

Also unless you have a pocket full of cash, going from FPGA to ASIC is typically prohibitive.

> the additional step to make it ready for silicon is comparatively small

Yep, you just change the target platform and re-compile!

"Comparatively small" is still several weeks of work, as far as I know.

There are tools targeting these languages. For instance, clash lets you write functional code and get verilog (iirc).