Show HN: A pipelined RISC-V processor written in VHDL

Re:Show HN: A pipelined RISC-V processor written in VHDL by _chris_ on Tuesday July 28, 2015 @06:12PM (#9964897)

It's actually really pretty easy to do. I put together a handful of different RISC-V cores that all implement the privileged/supervisor spec (https://github.com/ucb-bar/riscv-sodor/blob/master/src/rv32_...).

Basically, detect a few cases in Decode, pass the rest of the instruction down the pipeline to the commit(memory) stage, and let the commit stage detect exceptions and redirect the PC as required.

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Re:Show HN: A pipelined RISC-V processor written in VHDL by inforichland on Tuesday July 28, 2015 @09:05PM (#9965679)

Exactly, that's how I would (hopefully will soon) implement it as well; it takes a few extra cycles but avoids extra overhead.

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