Show HN: A pipelined RISC-V processor written in VHDL

Re:Show HN: A pipelined RISC-V processor written in VHDL by sklogic on Wednesday July 29, 2015 @04:42AM (#9967142)

Higher level generator HDLs shine when you want something heavily parametric. VHDL and Verilog code generation features are way too weak, so having a higher level meta-language helps a lot.

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