Here is an interesting (not) security feature: https://news.ycombinator.com/item?id=9956044

Not doing it fully during a procedure call is an optimization. I responded to the comment with links from 2002 and 2005 that showed this along with proper way to save everything to memory. Shouldn't have been a surprise to someone reading up on it.

So they used a securely designed component and got bit anyway.

That wasn't the security features. It was the features not designed for security and targeting an audience wanting performance enhancements. The kind of thing that often leads to unexpected problems. ;)

Yeah...the i960mx was a missed opportunity. It was certainly oversold as "Intels RISC replacement for x86" (it was never going to be that in the real world), but it would have been interesting to see how far it would have gone if the decision hadn't been "we'll just neuter the little bastard and try and recoup some development dollars by using it as an embedded processor".

""we'll just neuter the little bastard and try and recoup some development dollars by using it as an embedded processor"."

Lmao well-put. Maybe if they saw it worded that way on the drawing board they might have seen the folly. I keep thinking of checking on the Alpha ISA licensing situation to get PALcode, etc back. Last I checked Intel and Samsung had control of licensing but it kinda disappeared.

Might just stick with SPARC or RISC-V with modifications to use clever modifications from the past. Might even try to design a knock-off of i960's better features updates based on lessons learned over time.

I've been impressed with the RISC-V folks. Seem to have solid talent and realistic goals.

Did you mean the main University group (s) that defined and implemented the ISA? If so, I agree they've done well. I especially loved that they open-sourced a 1+GHz 48nm core. Awesome stuff.

I posted a link to Schneiers Squid thread today on a bunch of asynchronous chip work. One was a 180nm FPGA w/ several times Xilinx's performance and one a 40nm microcontroller. I imagine a combination of RISC-V with that async flow would produce one drool-worthy processor in price, performance, and NRE cost.

Can you point out where the links are?

Enjoy:

http://pastebin.com/bakX4RRZ

Thank you very much!

Yeah...that 1GHz core could be the game changer as far as Open Source hardware goes. Seems pretty much anyone with an above average undergrad digital design competency has cooked up a core/ISA that ranges from the few tens to a few hundred MHz, but a real 1GHz core on a real process potentially puts it in range of the ARM/MIPS crowd performance wise (that is, out of "isn't that a cute toy" territory).

I confess to not being particularly conversant with async design (it became mainstream after my time), but I'll definitely check out your links and see what I can learn.

Interesting times and all that.

More interesting than you think: we have an open-source FPGA architecture out there now and cheap[ish] processes to implement it.

http://pastebin.com/bakX4RRZ

I thank you, sir, for this months reading list.

You're welcome. I have over ten thousand in all and someone just asked me for dome on making C programs memory safe. So if you like that too check back on my profile's comments in a day or so.

That was me asking about memory safety, actually. You ever get to Atlanta, GA, I owe you a dinner and a beer.

Oh must have lost track lol. Appreciate it and might take you up on it.