Reference "The Boy who cried Wolf". That pronouncement has been made and proven wrong way too many times for anybody to take it seriously. Eventually the wolf will come and the limit will be reached, but until it happens nobody will believe it.

But how is this is possible? Diameter of silicon atom is 0.2nm and we need at least several atoms to create a transistor. I am sure Intel will be able to fulfill its roadmap to 4nm, maybe 2nm, but at this size quantum effects are so large, that everything should be changed.

Remember feature pitch, which is what the 14nm term measures, and layer thickness are two different things. The layers are way thinner than the feature pitch, so we're already at 1nm layer depths, or less, in some chips.

It'll be interesting to see the parts that silicon photonics and molecular assembly come to play in meeting the future process nodes.

I agree with those who say we'll reach a cost barrier before we reach a technical barrier. If I were to make a wild guess, I'd say 7nm will be that limit, and that it'll be about 5 years away (Moore's Law is already broken and isn't likely to be fixed any time soon, hence the slower timeframe).

A cost barrier is the most common manifestation of a technical barrier.

There's no way silicon microlitography will keep working once transistors are just a few atoms big. In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore.

>"There's no way silicon microlitography will keep working once transistors are just a few atoms big."

That's why I mentioned molecular assembly.

>"In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore."

That's why I mentioned silicon photonics.

> "A cost barrier is the most common manifestation of a technical barrier."

It can be, but not always. We can definitely move beyond 7nm, we've already done it in the lab, but knowing if we can find ways to afford the costs of manufacturing below that point is not as clear.

http://www.purdue.edu/newsroom/research/2012/120219KlimeckAt...

3D stacking. Heat dissipation is the limitation in this case, not the process size.

3D stacking won't solve heat dissipation problem, it will only worsen it. If we add N layers, we will increase heat in N times.

> But how is this is possible?

That's the question to answer. It's just as hard to prove that you CAN'T assemble a transistor of that size.

I'm curious, what are the quantum effects at that size?

See, for example, https://en.wikipedia.org/wiki/Quantum_tunnelling