Re:Intel's 10nm 'Cannonlake' delayed, replaced by 14nm 'Kaby...
by ZenoArrow on Monday July 06, 2015 @03:53PM
(#9841770)
>"There's no way silicon microlitography will keep working once transistors are just a few atoms big."
That's why I mentioned molecular assembly.
>"In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore."
That's why I mentioned silicon photonics.
> "A cost barrier is the most common manifestation of a technical barrier."
It can be, but not always. We can definitely move beyond 7nm, we've already done it in the lab, but knowing if we can find ways to afford the costs of manufacturing below that point is not as clear.
That's why I mentioned molecular assembly.
>"In fact, at 10 nm tunnel currents should be already a big problem on all sides of the transistors, and not constrained to the gate - channel insulation anymore."
That's why I mentioned silicon photonics.
> "A cost barrier is the most common manifestation of a technical barrier."
It can be, but not always. We can definitely move beyond 7nm, we've already done it in the lab, but knowing if we can find ways to afford the costs of manufacturing below that point is not as clear.
http://www.purdue.edu/newsroom/research/2012/120219KlimeckAt...