Xilinx invested heavily in TSMC's TSV interposer and likely their IN-FO fan-out packaging. These allow them to integrate more silicon area in the same package space. It can potentially offset the technology node gap, and maybe for lower cost. Yes, TSV is expensive, but a process node is even more expensive.

Multi-die FPGA packages are a giant PITA to deal with, compared to monolithic. It's a lot harder to resolve timing problems.

There's a small customer base that's already used to partitioning their designs across multiple FPGAs, and taking the huge performance hit from it (e.g., ASIC emulation). But for most, yeah... giant PITA.