DrHoppenheimer

Multi-die FPGA packages are a giant PITA to deal with, compared to monolithic. It's a lot harder to resolve timing problems.

There's a small customer base that's already used to partitioning their designs across multiple FPGAs, and taking the huge performance hit from it (e.g., ASIC emulation). But for most, yeah... giant PITA.

You're confusing OpenCL with high level synthesis (HLS). OpenCL is explicitly a platform for software developers. It targets accelerator boards attached to a host (via PCIE), just like GPGPU.

https://www.altera.com/solutions/partners/opencl-board-partn...

That's not how it works, actually. The compiler generates the dataflow directly in hardware.