craigjb

For chips with integrated CPU+GPU+NPU, it could be worth it tech-wise. The GPU and NPU can eat HBM bandwidth. For general purpose CPU code, the HBM would likely not be worth it. It's high bandwidth, but you trade latency, and general CPU code is branchy. Economics-wise, the HBM stacks alone will cost more than a consumer CPU (or APU).

[edit] The packaging needed to support HBM is also much more expensive too. If demand for current HBM applications tanks and the manufacturing lines need filled, then maybe. Currently, the price point would make it very very niche.

HBM4 has over 2048 signals to the processor’s PHY with tight signal integrity requirements that require the HBM stack to be < 0.5 mm from the processor die. That’s why HBM integration is done with interposers (soldered on the package). So, it’d be the CPU package that integrates it. Motherboard is too far away.

We’re at approximately where PCB pricing was 20 years ago, which _is_ a big deal: https://wafer.space

Apple has not shipped an InFO-PoP with side-by-side integrated die yet. This is expected to be the first one, using RDLs for the die-to-die interconnect (so different than M-Ultra series that uses silicon bridges).

Applied Materials, Lam Research, and KLA are all U.S. companies. ASML supplies lithography, but hundreds of other tools come from these companies.

The terms to search for are fan-out wafer level packaging (FOWLP) and TSMC InFO. The chiplets come from different wafers and are reconstituted into a molded plastic wafer, allowing multiple die side-by-side. Then multiple layers of wires are built on top, terminating in a BGA.

7nm for Achronix

https://www.achronix.com/product/speedster7t-fpgas

Equipment for ion implantation already includes mini accelerators [1] [2]. The semiconductor equipment industry in general has many machines that feel like they came out of a physics lab into a semi fab. For example, plasma dry-etching or deep-reactive ion etching. EUV litho is just one of many very interesting problems--currently the bottleneck so it's talked about a lot.

[1] https://en.wikipedia.org/wiki/Ion_implantation [2] https://www.axcelis.com/products/purion-xe-series-high-energ...

edit: add link to cool ion implanter machine pics

You also need hundreds of other machines from Applied Materials, KLA Tencor, Lam Research, Tokyo Electron, etc. Then, years of process development R&D: what temperature do we bake this layer at, how long, what profile, what atmosphere in the tool… Every process step has a large parameter set to optimize. Creating a process is a painstaking many many variable optimization slog.

Just wanted to add that since I see people only mention ASML often here. They are very important, but there is so much more to TSMC’s success.

You are absolutely correct that design costs swamp mask costs by far. For 7 nm, it costs more than $271 million for design alone (EDA, verification, synthesis, layout, sign-off, etc) [1], and that’s a cheaper one. Industry reports say $650-810 million for a big 5 nm chip.

[1] https://semiengineering.com/racing-to-107nm/

I built the Gameslab around this concept, but haven’t worked on it much lately.

https://craigjb.com/2019/11/26/gameslab-overview/

Keep in mind, a semiconductor fab has hundreds of other machines and equipment involved, and US companies are some of the biggest suppliers (Applied Materials, Lam Research, KLA-Tencor--all multi-billion dollar companies).

Lithography is definitely key, but all the equipment and process must work together.

TSMC's plans for Arizona have been increased to start with 100k per month with future phases up to 200k [1]

[1] https://technosports.co.in/2021/03/03/tsmc-to-build-5nm-plan...

The ASML lithography machine is just one, very important, machine out of many dozens. A semiconductor fab process involves 100s-1000s of process steps each with dozens to hundreds of parameters. For example, something as simple as rinsing a wafer after an etch step:

- How long to rinse

- What to rinse with (DI water, solvent, etc)

- What temperature to rinse at

- Should the temperature change over time?

- Agitated vs. non-agitated

It may sound small, but a bad rinse process will tank yields and make the whole process fail.

In a huge semiconductor company like Intel or TSMC, multiple process engineers specialize on each one of these steps out of hundreds. These are truly massive undertakings.

Microchip has the product for you then! Well, the RiscV part anyway. https://www.microsemi.com/product-directory/soc-fpgas/5498-p...