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A comment on DDR4 memory interface. Parent comment

Re:DDR4 memory interface by tcas on Friday July 25, 2014 @11:11AM (#8085596)
SDRAM's interface doesn't leave room for extra commands, it's pretty much designed to read/store data and refresh content. It only has 3 lines to select the command (RAS#, CAS#, WE#).

Other RAMs/Flash with different interfaces (e.g. SPI) require a prefix command to be sent over the wire, so it's easier for them to implement things like chip id commands.

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Re:DDR4 memory interface by kenz0r on Saturday July 26, 2014 @04:53AM (#8089255)
I don't think that is exactly true. DRAM from SDRAM up has had a number of mode registers to control the ram. More info here: http://en.wikipedia.org/wiki/Synchronous_dynamic_random-acce...
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Re:DDR4 memory interface by cnvogel on Saturday July 26, 2014 @10:01AM (#8089751)
Exactly. ...here's the table for command accesses on DDR4, including the mode register you referred to.

http://en.wikipedia.org/wiki/DDR4_SDRAM#Command_encoding

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