Re:DDR4 memory interface
by bodyfour on Friday July 25, 2014 @04:43AM
(#8084259)
That actually surprises me.. I would have guessed that there would be some amount of metadata you could query over the data lines, such as the specs for the DIMM. I guess that's all sent over I2C or something instead?
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Yeah, that's all done through a seperate EEPROM chip accessed over SMBUS, which is essentially the same as I2C. Raw SDRAM chips don't provide any way to query their specification; on embedded systems that use them, the settings are generally all hardcoded in the bootloader.
SDRAM's interface doesn't leave room for extra commands, it's pretty much designed to read/store data and refresh content. It only has 3 lines to select the command (RAS#, CAS#, WE#).
Other RAMs/Flash with different interfaces (e.g. SPI) require a prefix command to be sent over the wire, so it's easier for them to implement things like chip id commands.
I don't think that is exactly true.
DRAM from SDRAM up has had a number of mode registers to control the ram. More info here: http://en.wikipedia.org/wiki/Synchronous_dynamic_random-acce...
Exactly. ...here's the table for command accesses on DDR4, including the mode register you referred to.