Re:RISC-V Is Inevitable: State of the Union Keynote Argues
by seastarer on Wednesday July 15, 2026 @05:51AM
(#48918439)
You can try to re-vectorize the code for larger vector size.
Re:RISC-V Is Inevitable: State of the Union Keynote Argues
by diamondlovesyou on Wednesday July 15, 2026 @06:08AM
(#48918551)
Not if you can't prove anti-aliasing properties, which wasm doesn't carry.
Re:RISC-V Is Inevitable: State of the Union Keynote Argues
by Someone on Wednesday July 15, 2026 @07:32AM
(#48919244)
I don’t think the OP is starting from WASM code; they’re starting from a language with SIMD primitives that map closely to those of WASM. There, you often have information to prove function arguments do not alias.
On the one hand, this will be quite straight forward, but on the other hand quite disappointing.
Afaik Dart has a 128-bit only SIMD abstraction (so not performance portable by default). Since the base "V" extension mandates a mininum vector length of 128-bit, you can trivially make codegen work for all vector length, by simply setting vl to 128/elementwidth.
But as with x86, if your native hardware vector length is larger than 128-bit, you leave performance on the table.
> This is mostly because their approach to SIMD is so different, but also because I can't test it at all. Are there any RISC-V "machines"?
I'd recommend using qemu for initial testing.
Hardware wise, the cheapest option is the orange pi rv2, which has 8 SpacemiT X60 cores, which are in-order and support 256-bit RVV. The Zhihe A210 is also interesting, but way to expensive for what it is.
If you have a higher budget, I'd recommend the SpacemiT K3, which is the fist RISC-V SBC with RVA23 support. It is has 8 SpacemiT X100 4-wide out-of-order cores, with 256-bit RVV.