RISC-V Is Sloooow

Re:RISC-V Is Sloooow by hackyhacky on Tuesday March 10, 2026 @05:57PM (#47329291)

> One of the best parts about RiscV is that you can teach a freshman level architecture class or a senior level chip building project with an ISA that is actually used.

Same could be said of MIPS.

My understanding is the RISC-V raison d'etre is rather avoidance of patented/copywritten designs.

[ Parent | on HN ]

Re:RISC-V Is Sloooow by adgjlsfhk1 on Tuesday March 10, 2026 @06:10PM (#47329407)

the avoidance of patent/copyright is critical for (legally) having students design their own chips. MIPS was pretty good (and widely used) for teaching assembly, but pretty bad for teaching a class where students design chips

[ Parent | on HN ]

Re:RISC-V Is Sloooow by userbinator on Wednesday March 11, 2026 @12:10AM (#47331667)

MIPS patents have long expired too (and incidentally for any other CPU released prior to 2006), so that's a moot point.

[ Parent | on HN ]

Re:RISC-V Is Sloooow by musicale on Wednesday March 11, 2026 @12:14AM (#47331695)

This is largely disproven by the pre RISC-V, MIPS editions of Patterson & Hennessy and Harris & Harris, etc., which teach you how to design a MIPS datapath (at the gate level.)

[ Parent | on HN ]

Re:RISC-V Is Sloooow by musicale on Wednesday March 11, 2026 @12:12AM (#47331683)

As you probably know, MIPS was widely used in computer architecture courses and textbooks, including pre-RISC-V editions of Patterson & Hennessy (Computer Organization & Design) and Harris & Harris (Digital Design and Computer Architecture.

In spite of the currently mediocre RISC-V implementations, RISC-V seems to have more of a future and isn't clouded by ISA IP issues as you note.

[ Parent | on HN ]