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Re:RISC-V Is Sloooow by rbanffy on Tuesday March 10, 2026 @04:30PM (#47328435)
> At this point the most likely place for fast RISC-V to appear is China.

Or we just adopt Loongson.

Re:RISC-V Is Sloooow by balou23 on Tuesday March 10, 2026 @04:48PM (#47328613)
TBH I still don't really get how it's different from MIPS. As far as I can tell... Loongson seems to be really just MIPS, while LoongArch is MIPS with some extra instructions.
Re:RISC-V Is Sloooow by bonzini on Tuesday March 10, 2026 @05:47PM (#47329188)
LoongArch is, on a first approximation, an almost RISC-V user space instruction set together with MIPS-like privileged instructions and registers.
Re:RISC-V Is Sloooow by mananaysiempre on Tuesday March 10, 2026 @07:35PM (#47330140)
Wait, this is a modern-ish ISA with a software-managed TLB, I didn’t realize that! The manual seems a bit unhappy about that part though:

> In the current version of this architecture specification, TLB refill and consistent maintenance between TLB and page tables are still [sic] all led by software.

https://loongson.github.io/LoongArch-Documentation/LoongArch...

Re:RISC-V Is Sloooow by bonzini on Wednesday March 11, 2026 @03:28AM (#47332605)
I think they have already added hardware page table walks.

https://lwn.net/Articles/932048/

Re:RISC-V Is Sloooow by pantalaimon on Tuesday March 10, 2026 @05:38PM (#47329099)
They did get rid of the delay slots and some other MIPS oddities
Re:RISC-V Is Sloooow by mananaysiempre on Tuesday March 10, 2026 @04:57PM (#47328694)
But legally distinct! I guess calling it M○PS was not enough for plausible deniability.
Re:RISC-V Is Sloooow by genxy on Tuesday March 10, 2026 @05:15PM (#47328864)
ISAs shouldn't be patentable in the first place.
Re:RISC-V Is Sloooow by throawayonthe on Tuesday March 10, 2026 @05:37PM (#47329089)
(purely on vibes) loongson feels to me like an intermediate step/backup strategy rather than a longterm target (though they'll probably power govt equipment for decades of legacy either way :p)