Tenstorrent is supposedly taping out 8-wide Ascalon processors as we speak, with devboards projected to be available in Q2/Q3 this year.

BTW. Keller is also on the board for AheadComputing — founded by former Intel engineers that had been behind the fabled "Royal Core".

>Ascalon tape out

Supposedly happened earlier this year. Tenstorrent says devboards in Q3.

Now we just wait.

I can't know what Ascalon will actually be, but back in April/May 2025 there were actual performance numbers presented by Tenstorrent, and I analyzed what was shown. I concluded that Ascalon would be the x86_64 equivalent of an i5-9600K.

That's useable for many applications, but it's not going to change the world. A lot of "micro PCs" with low power CPUs are well past that now. If that's what Ascalon turns out to be, it will amount to an SBC class device.

I don't know what bubble you are living in, but the i5-9600K is many steps up beyond "SBC class".

The Raspberry Pi 5 results on Geekbench 6 are all over the place. A score between 500 to 900 in single core and a 2000 multi core score.

Radxa 4 is an SBC based around the N100 and it basically gets the same or slightly higher performance as the Raspberry Pi 5.

Meanwhile the i5-9600K gets a score of 1677 in single core, which is 83% of the performance of the entire Raspberry Pi 5 and gets a score of 6199 when using multiple cores, that's 3x the performance.

I'd call this at least "Laptop class" and you even admitted yourself back in 2025 that you're using a processor on that level.

"I don't know what bubble you are living in"

My bubble includes a number of SBCs and embedded boards from Advantech, most with Ryzen embedded (V1000 class) CPUs.

SBC is too vague I suppose. Past the hobbyist level of SBC, there are many* vendors with Core i5-1340P and similar CPUs today. These are superior to a 2018 i5-9600k. That's a 2023 device, which aligns with what I concluded at the time.

In 2025+, such a CPU is not a desktop class device, and is sufficient in a modest laptop in lower power form. I use one for light Linux development work.

* LattePanda Sigma, ASROCK NUC, DFROBOT, Premio and many NAS and industrial devices.

> At this point the most likely place for fast RISC-V to appear is China.

Or we just adopt Loongson.

TBH I still don't really get how it's different from MIPS. As far as I can tell... Loongson seems to be really just MIPS, while LoongArch is MIPS with some extra instructions.

LoongArch is, on a first approximation, an almost RISC-V user space instruction set together with MIPS-like privileged instructions and registers.

Wait, this is a modern-ish ISA with a software-managed TLB, I didn’t realize that! The manual seems a bit unhappy about that part though:

> In the current version of this architecture specification, TLB refill and consistent maintenance between TLB and page tables are still [sic] all led by software.

https://loongson.github.io/LoongArch-Documentation/LoongArch...

I think they have already added hardware page table walks.

https://lwn.net/Articles/932048/

They did get rid of the delay slots and some other MIPS oddities

But legally distinct! I guess calling it Ｍ○ＰＳ was not enough for plausible deniability.

ISAs shouldn't be patentable in the first place.

(purely on vibes) loongson feels to me like an intermediate step/backup strategy rather than a longterm target (though they'll probably power govt equipment for decades of legacy either way :p)