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A comment on Designing a Low Latency 10G Ethernet Core (2023). Parent comment

Re:Designing a Low Latency 10G Ethernet Core (2023) by Perz1val on Thursday October 09, 2025 @03:24AM (#45524587)
Not my are of expertise, but afaik the neat part is that you don't do it in cycles. The "program" lives as the transistor layout, not as instructions
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Re:Designing a Low Latency 10G Ethernet Core (2023) by wtallis on Thursday October 09, 2025 @03:27AM (#45524601)
The cycles in question are not those of any processor, but those of the signal coming in the wire. No matter how it's implemented, a switch cannot react to bits that are still in the wire and haven't made it to the switch yet.
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