Re:Designing a Low Latency 10G Ethernet Core (2023)
by rasz on Thursday October 09, 2025 @03:06AM
(#45524478)
Cut Through switching needs what, 14 bytes? Thats ~12ns on 10G? How would you do it in 40 cycles?
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Re:Designing a Low Latency 10G Ethernet Core (2023)
by Perz1val on Thursday October 09, 2025 @03:24AM
(#45524587)
Not my are of expertise, but afaik the neat part is that you don't do it in cycles. The "program" lives as the transistor layout, not as instructions
Re:Designing a Low Latency 10G Ethernet Core (2023)
by wtallis on Thursday October 09, 2025 @03:27AM
(#45524601)
The cycles in question are not those of any processor, but those of the signal coming in the wire. No matter how it's implemented, a switch cannot react to bits that are still in the wire and haven't made it to the switch yet.
Re:Designing a Low Latency 10G Ethernet Core (2023)
by ongy on Thursday October 09, 2025 @04:34AM
(#45525046)
why do you assume the full ethernet header?
IIRC. cut-through only needs the first 6 bytes. Since it only needs the destination address for the port lookup.
Potentially the first bit, on broadcast.
Re:Designing a Low Latency 10G Ethernet Core (2023)
by rasz on Thursday October 09, 2025 @05:41AM
(#45525479)
Because you might want VLAN. Plus you cant just start blasting reply without a preamble, so its still 14 bytes after receiving just the dest MAC. Then you get potential IFG, FEC, scrambling, it all adds up, no way any switch can do 4ns without heavy lawyer talk in the small print.