The closest you'll get is xc7 (Xilinx) vs vendor, one of which is surely Xilinx 7. But the Yosys xc7 support is limited and not the best supported, so it's not a great comparison either.
https://github.com/siliconcompiler/logiklib/tree/main/logikl...
https://github.com/zeroasiccorp/wildebeest/tree/main/archite...
Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)
Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.
We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)
[1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the reported results with a huge grain of salt.