I agree this is very "FPGA-shaped" and I wonder if they have further switching optimisations on hand.

My understanding is that they have a grid configuration cache, and are certainly trying to reduce the time/power cost of changing the grid connectivity.

An FPGA startup called Tabula had the same thesis and it didn't work out well for them. Their configurable blocks had 16 configurations that they would let you cycle through. Reportedly, the chips were hell to program and the default tools were terrible.

Is that a design flaw or a tooling flaw? The dev experience is usually left till the very end of some proof like this.

It doesn't matter. You have to get both right or you go out of business.

(And then your IP is thrown away so the next startup also has to get both right...)

Yeah, merely asking for posterity in case someone wants to iterate on it. The dev tools need just as much attention as the hardware. Sometimes the community can surprise you. Take fritzing for example. I think the hardware design is novel but to benchmark it fully requires dev tooling that knows how to utilize it all, and in such a way that it abstracts those details from the average developer.

A good example of this is abstracting SIMD instructions for vector multiplication, or CUDA with torch. Normal people don’t care how it’s done, only that it’s done, as fast as can be done.

Both? Theoretically amazing hardware that just needs the magic compiler to work well is a well worn path in the hardware world (The itanium being a notable example). A design can be impossible to compile well for and very hard to program manually if it hasn't been developed well. Equally you can indeed have a bad toolchain for that hard to use design making it even harder to get the best out of it.

I'm thinking of the Sony Toshiba IBM Cell processor. In the end with experience you could deliver impressive performance and the lessons learned proved to be valuable on any multi core system. But everyone knows the reputation that the PS3 had and certainly in retrospect it was challenging to say the least.

Nah, the issue with PS3 was everyone coming from a specific set of instructions and having, that, hard wired into their brains. Yes, the cell processor did things differently but it was us engineers who had to learn to think of a world beyond x86. This was a good thing. It let us learn. And when Arm came around, we were ready.

Very much agree. It was a positive experience.

Yeah, I have worked with FPGAs a while ago and still casually follow the space.

There have been many attempts of mapping general purpose/GPU programming languages to FPGA and none of them worked out.

The first leading claim they make - that this is a general purpose CPU, capable of executing anything - I suspect is false.

CPUs are hard because they have to interact with memory, basically 95% of CPU design complexity comes from having to interact with memory, and handling other data hazards.

If this was reducible complexity, they'd have done so already.

Then I have a thought experiment. Replace the execution cores on a state of the art GPU and CPU with FPGAs.

See amdahls law Edit: [0] https://en.m.wikipedia.org/wiki/Amdahl%27s_law

Yes but we are also talking about energy efficiency

See figure 1 in [0] operation execution is just 0.1pj of 70pj required for a 32 bit int addition… how do you think I was applying amdahls law? Edit: I was using amdahls law as it applies to parallel processors. However in terms of energy usage …

See amdahls laws and use your imagination [0] https://semiengineering.com/more-data-drives-focus-on-ic-ene...

See 'Apple-Core', Microgrids, SVP, UTLEON3

In theory, in practice this seems to have failed, but still...

Also related: https://www.microsoft.com/en-us/research/project/emips/

In academia people use general purpose languages (Notably C++ dialects) for FPGA design quite a lot. And there's definitely a glut of papers published on the development of such "High Level Synthesis" tools.

In order to use the FPGA efficiently you need to first pipeline the logic deeply, but then also be able to fill that pipeline.

But in my opinion there is just too much of an impedance mismatch between the "do one thing and then the next" style of imperative code, and the "everything everywhere all at once" way in which FPGAs actually work.

And well, here's my plug for my language that gets close to HLS in terms of syntactic ease, while still retaining full control over the generated hardware: https://github.com/pc2/sus-compiler

By explicitly keeping track of pipelining in submodules the compiler automatically balances the pipelines your create, and in addition, you can write modules that respond to the pipeline distance between their ports, and infer their parameters based on that. That fixes one of the most error-prone activities when designing hardware in SV or other languages.

I worked in industry, trying to fit video processing algorithms and filter banks to FPGAs, about a decade ago, so my memories are a bit fuzzy.

The thing about FPGAs is that they are wildly expensive, getting exponentially more so the more you move up the product pallette. They also have a ton of special function blocks (DPRAM, multipliers, shift registers etc), that work differently from vendor to vendor, and even between generations.

Even with HDLs you had to options - either read all the datasheet, the layout and mix of components, and plan your design to fit the hardware - or just wing it and write down what you wanted, and hope for the best - in the latter scenario, the synthesis tool had to figure out how to fit your design best to the hardware, which even if you were mindful of how the chip worked, was still a hit and miss.

When you work in industry and either every cent counts, or you have to design for a fixed target, and somehow you're in the good graces of tooling, finding that changing a small thing suddenly makes your design 3x as big and half as fast is not acceptable.

HLS was this, but on steroids - you never knew what you were going to get, sometimes it worked well, sometimes not at all.

I'm sure tooling has evolved back then but I'd still guess spending the extra engineering effort is often well worth it when your chips cost five figures.

Yup, HLS is ridiculously fickle in that regard. In our lab we had the case that swapping out a C-style array T[] for a C++ std::array 10x-ed our resource consumption with no explanation.

And also the general problem of scribing resource use to the different components isn't easy, because thz way control flow is structured heavily alters that

Of course, that's what I'm trying to fix with SUS :p

I recall Mathstar's FPOA (field programmable object arrays) have had similar architecture. it seems they have done a mixture of stack computer, this and some async programming to get this level of optimization. The other one I had seen with pretty good on chip fabric was Tilera who were using something like a packet switch to interconnect tonnes of on-chip cores.

My first reaction watching this video was that they are just shifting the problem to compiler, which is actually worse and also does not works for dynamic code with tonnes of branches. Also, didnt Intel burn a lot of money trying to do this with Itanium?

Overall, interesting idea but I filed it under 'solution looking for a problem' desk.