Building the System/360 Mainframe Nearly Destroyed IBM

Re:Building the System/360 Mainframe Nearly Destroyed IBM by graycat on Wednesday April 09, 2025 @06:16AM (#43630578)

> the entire world circa 1970.

About then was the IBM 360/91 with a 60 nanosecond cycle time. So, that would be a clock speed of

     1/ ( (60)/(10^9) ) 

     = (10^9) / 60

     = 10^7 (100 / 60 )

     = 10^7 (10 / 6 )

     = 10^7 (1.66)

     1.66 (10,000,000)

     16.66 (1,000,000)

     = 17 Mhz

Now we can have clock frequencies of 4 GHz, that is

     4000/17 = 235

times faster. And we can have 16 cores instead of 1 for

     (16)(4000) / 17 = ~4000

times faster. "entire world"?

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Re:Building the System/360 Mainframe Nearly Destroyed IBM by photon_rancher on Thursday April 10, 2025 @03:05AM (#43641437)

What’s the average IPC of these chips for a reasonable workload?

Early processors were typically 1 or lower. Modern stuff is all superscalar piplined and out of order and can do way more than you’d expect. Not to mention SIMD operations and other technologies. Branch prediction is probably better on the new chips too.

And with more RAM and cache algorithms can be chosen with different tradeoffs for less instructions.

16 cores at 4ghz was a thing like a decade ago - chips today might have the same specs but are definitely far faster.

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Re:Building the System/360 Mainframe Nearly Destroyed IBM by graycat on Thursday April 10, 2025 @09:42PM (#43649664)

WOW! IPC, instructions per cycle? Sure, back in those days, usually how many cycles per instruction! The 360/91 was a high end thing, said to cost $13 million. One was at the Navy lab, JHU.APL. As I recall, it could do 1 floating point (32 or 64 bits?) instruction per cycle and sometimes 3 in 2 cycles.

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