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A comment on A FPGA friendly 32 bit RISC-V CPU implementation. Parent comment

Re:A FPGA friendly 32 bit RISC-V CPU implementation by teleforce on Monday January 27, 2025 @03:10AM (#42838616)
> There was an attempt to make a kind of IR for RTL that would break the tie with SV

It's probably FIRRTL and CIRT is the compiler for that [1], [2].

[1] The specification for the FIRRTL language:

https://github.com/chipsalliance/firrtl-spec

[2] Original FIRRTL compiler that's now been replaced by CIRT:

https://github.com/chipsalliance/firrtl

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by IshKebab on Monday January 27, 2025 @04:29AM (#42839095)
Ah no I found it: https://github.com/fabianschuiki/llhd

It does seem to be part of CIRCT in some way though. Maybe it inspired FIRRTL or something. Slightly unclear relationship between the projects!

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