A FPGA friendly 32 bit RISC-V CPU implementation

Re:A FPGA friendly 32 bit RISC-V CPU implementation by IshKebab on Sunday January 26, 2025 @05:26PM (#42834849)

Basically no. Almost everybody uses SystemVerilog. The main issue is that all the simulators only support SystemVerilog so every other HDL is compile-to-SV, and often they output truly awful code that is a nightmare to debug.

Also SV has an absolutely enormous feature set, and often alternative HDLs miss out important parts like support for verification, coverage, formal verification, etc.

Getting away from SV is like getting away from JavaScript. The network effects are insane.

There was an attempt to make a kind of IR for RTL that would break the tie with SV (kind of like WASM has for JS)... I can't remember the name (LL..something?) but it seemed to have died.

Maybe this is similar I'm not sure: https://github.com/llvm/circt

Anyway the only really interesting new HDL I've seen is https://filamenthdl.com/

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by teleforce on Monday January 27, 2025 @03:10AM (#42838616)

> There was an attempt to make a kind of IR for RTL that would break the tie with SV

It's probably FIRRTL and CIRT is the compiler for that [1], [2].

[1] The specification for the FIRRTL language:

https://github.com/chipsalliance/firrtl-spec

[2] Original FIRRTL compiler that's now been replaced by CIRT:

https://github.com/chipsalliance/firrtl

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Re:A FPGA friendly 32 bit RISC-V CPU implementation by IshKebab on Monday January 27, 2025 @04:29AM (#42839095)

Ah no I found it: https://github.com/fabianschuiki/llhd

It does seem to be part of CIRCT in some way though. Maybe it inspired FIRRTL or something. Slightly unclear relationship between the projects!

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