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A comment on Intel's $475M error: the silicon behind the Pentium division bug. Parent comment

Re:Intel's $475M error: the silicon behind the Pentium divis... by Sesse__ on Sunday December 29, 2024 @05:30PM (#42544015)
> FMUL could only be issued every other cycle, which made scheduling even more annoying.

Huh, are you sure? Do you have any documentation that clarifies the rules for this? I was under the impression that something like `FMUL st, st(2) ; FXCH st(1), FMUL st, st(2)` would kick off two muls in two cycles, with no stall.

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Re:Intel's $475M error: the silicon behind the Pentium divis... by Tuna-Fish on Sunday December 29, 2024 @05:52PM (#42544234)
Agner Fog's manuals are clear on this. Only the last of FMUL's 3 cycles can overlap with another FMUL.

You can immediately overlap with a FADD.

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