Re:Intel's $475M error: the silicon behind the Pentium divis...
by Sesse__ on Sunday December 29, 2024 @05:30PM
(#42544015)
> FMUL could only be issued every other cycle, which made scheduling even more annoying.
Huh, are you sure? Do you have any documentation that clarifies the rules for this? I was under the impression that something like `FMUL st, st(2) ; FXCH st(1), FMUL st, st(2)` would kick off two muls in two cycles, with no stall.
Compilers got pretty good at optimizing straight line math but were not as good at cases where variables needed to be kept in the stack during a loop, like a running sum. You had to get the order of exchanges just right to preserve stack order across loop iterations. The compilers at the time often had to spill to memory or use multiple FXCHs at the end of the loop.