They've made some details public about their architecture [1] and even their RISC-V test suite [2] but I'd also love to know what it was referring to.

[1] https://www.theregister.com/2024/08/27/tenstorrent_ai_blackh...

[2] https://github.com/tenstorrent/riscv_arch_tests

I'm hoping we at least get pshufb, aesenc, rep movsb, some sort of integer multiply, and a floating point fma

I would say it's load, store, compare, add, subtract, call, return and branch. If you have that you cover almost all code.

Implementing multiplies as a bunch of adds has got to suck for performance though.

Well, if you decompose it to a series of shifts and adds, it’s a bit quicker. That’s actually how the 8086 implemented it.

Sure. Multiplication is exceedingly rare compared to any of those 8 instructions though. RISC-V base instruction set doesn't include multiplication for example. If you had room to add more then 8 I would rather add the bitops first. This will allow you to also write a much more efficient soft mul in addition to many more things.