That's an older article from when TLC (3bit) NAND launched, but the principles are the same for QLC (4bit).

Nowadays SLC and MLC are barely used because TLC is good enough for nearly all purposes.

Some SSD controllers will also reassign regions of flash to different modes on the fly, the drives unused capacity can be used internally as a very fast pSLC write cache, and then as the drive fills up those cells incrementally get switched over to the native TLC/QLC mode.

This is very interesting. Thank you.

If you want to do it in a single step, you need 8 analogic comparators at the output of the memory, and one level of "and" and "or" gates to solve each bit.

Most ADCs use a single comparator + OpAmp and convert the value in 3 steps. But that would make your memory slower.

Either way, the task of converting it does not fall over the controller.