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Re:TSMC unveils 1.6nm process technology with backside power... by ReptileMan on Thursday April 25, 2024 @10:02AM (#40157717)
Not understanding chip design - but is it possible to get more computational bang with less transistors - are there some optimizations to be had? Better design that could compensate for bigger nodes?
Re:TSMC unveils 1.6nm process technology with backside power... by 7thpower on Thursday April 25, 2024 @11:11AM (#40158507)
Yes, generally one of the trends has been movement toward specialized coprocessors/accelerators. This was happening before the recent AI push and has picked up steam.

If you think of an SOC, the chip in your phone, more and more of the real estate is being dedicated to specialized compute (AI accelerators, GPUs, etc. vs general purpose compute (CPU).

At the enterprise scale, one of the big arguments NVIDIA has been making, beyond their value in the AI market, has been the value of moving massive, resource intense workloads from CPU to more specialized GPU acceleration. In return for the investment to move their workload, customers can get a massive increase in performance per watt/dollar.

There are some other factors at play in that example, and it may not always be true that the transistors/mm^2 is always lower, but I think it illustrates the overall point.

Re:TSMC unveils 1.6nm process technology with backside power... by merb on Thursday April 25, 2024 @02:18PM (#40161132)
JavaScript accelerator would probably half the power consumption of the world. The problem is just, that as soon as it would have widespread usage it would probably already be too old.
Re:TSMC unveils 1.6nm process technology with backside power... by robocat on Thursday April 25, 2024 @03:38PM (#40162035)
Reminiscent of the Java CPUs: Not even used for embedded (ironically the reason Java was created?). And not used at all by the massive Java compute needed for corporate software worldwide?
Re:TSMC unveils 1.6nm process technology with backside power... by crote on Thursday April 25, 2024 @05:41PM (#40163392)
Weren't they used in Java Cards?

Basically, every single credit card sized security chip (including actual credit cards, of course) is a small processor running Java applets. Pretty much everyone has one or more in their wallet. I'd assume those were actual Java CPUs directly executing bytecode?

Re:TSMC unveils 1.6nm process technology with backside power... by robocat on Thursday April 25, 2024 @09:54PM (#40165129)
> Weren't they used in Java Cards?

Not sure: https://en.wikipedia.org/wiki/Java_processor doesn't seem to mention any in current use. I am ignorant of the actual correct answer: I had simply presumed it is simpler to write the virtual machine using a commercial ISA than to develop a custom ISA.

  Java Card bytecode run by the Java Card Virtual Machine is a functional subset of Java 2 bytecode run by a standard Java Virtual Machine but with a different encoding to optimize for size.
https://en.wikipedia.org/wiki/Java_Card_OpenPlatform has some history but nothing jumped out to answer your question.
Re:TSMC unveils 1.6nm process technology with backside power... by greenavocado on Thursday April 25, 2024 @10:40PM (#40165422)
picoJava processors (Sun Microsystems) https://www.cnet.com/culture/sun-releases-complete-chip-desi...

Patriot Scientific's Ignite processor family https://www.cpushack.com/2013/03/02/chuck-moore-part-2-from-...

ARM Jazelle technology https://developer.arm.com/documentation/ddi0222/b/introducti...

https://www.eetimes.com/nazomi-offers-plug-in-java-accelerat...

It's all dot-com era stuff and Sun Microsystems also created a Java OS that could run directly on hardware without a host operating system.

That's about it

Re:TSMC unveils 1.6nm process technology with backside power... by greenavocado on Thursday April 25, 2024 @10:35PM (#40165401)
No, credit cards do not have CPUs or run Java code.
Re:TSMC unveils 1.6nm process technology with backside power... by choilive on Thursday April 25, 2024 @02:57PM (#40161587)
I believe ARM has some instructions that is JavaScript specific so we're kinda in that direction already.
Re:TSMC unveils 1.6nm process technology with backside power... by merb on Thursday April 25, 2024 @03:48PM (#40162157)
Yeah the https://developer.arm.com/documentation/dui0801/h/A64-Floati... but a full jit helper that is generalized is way way harder and as said will take a long time tobe generally available. Just look at wasmgc and that only has the minimum denominator.
Re:TSMC unveils 1.6nm process technology with backside power... by zeusk on Thursday April 25, 2024 @08:33PM (#40164696)
Back in the day, they supported byte code execution - https://en.wikipedia.org/wiki/Jazelle
Re:TSMC unveils 1.6nm process technology with backside power... by mort96 on Thursday April 25, 2024 @10:08AM (#40157799)
In general, yes, but all the chip design companies have already invested a whole lot of time and engineering resources into squeezing as much as possible from each transistor. But those kinds of optimizations are certainly part of why we sometimes see new CPU generations released on the same node.
Re:TSMC unveils 1.6nm process technology with backside power... by pjc50 on Thursday April 25, 2024 @11:26AM (#40158686)
Everyone generally does that before sending the design to the fab.

Not to say that improvements and doing more with less are impossible, they probably aren't, but it's going to require significant per design human effort to do that.

Re:TSMC unveils 1.6nm process technology with backside power... by pixelpoet on Thursday April 25, 2024 @10:07AM (#40157787)
Such optimisation would apply equally to the more dense processes, though.
Re:TSMC unveils 1.6nm process technology with backside power... by potatolicious on Thursday April 25, 2024 @11:31AM (#40158749)
Some yeah, but many of these optimizations aren't across-the-board performance improvements, but rather specializations that favor specific kinds of workloads.

There are the really obvious ones like on-board GPUs and AI accelerators, but even within the CPU you have optimizations that apply to specific kinds of workloads like specialized instructions for video encode/decode.

The main "issue", such as it is, is that this setup advantages vertically integrated players - the ones who can release software quickly to use these optimizations, or even going as far as to build specific new features on top of these optimizations.

For more open platforms you have a chicken-and-egg problem. Chip designers have little incentive to dedicate valuable and finite transistors to specialized computations if the software market in general hasn't shown an interest. Even after these optimizations/specialized hardware have been released, software makers often are slow in adopting them, resulting in consumers not seeing the benefit for a long time.

See for example the many years it took for Microsoft to even accelerate the rendering of Windows' core UI with the GPU.

Re:TSMC unveils 1.6nm process technology with backside power... by jjk166 on Thursday April 25, 2024 @01:31PM (#40160559)
The design optimization software for modern semiconductors is arguably the most advanced design software on earth with likely tens if not hundreds of millions of man-years put into it. It takes into account not only the complex physics that apply at the nano-scale but also the interplay of the various manufacturing steps and optimizes trillions of features. Every process change brings about new potential optimizations, so rather than compensating for bigger nodes it actually widens the gap further. By analogy, the jump from hatchet to scalpel in the hands a layman is far less than the jump from hatchet to scalpel for a skilled surgeon.
Re:TSMC unveils 1.6nm process technology with backside power... by kjkjadksj on Thursday April 25, 2024 @02:56PM (#40161572)
What about the effect of heat? More transistors per area equate a hotter chip, no?
Re:TSMC unveils 1.6nm process technology with backside power... by robocat on Thursday April 25, 2024 @03:40PM (#40162063)
More transistors switching I thought? It isn't about raw transistors e.g. memory isn't as power hungry as GPU?
Re:TSMC unveils 1.6nm process technology with backside power... by polishdude20 on Thursday April 25, 2024 @09:56PM (#40165145)
How is this kind of software developed without becoming a massive pile of spaghetti code?
Re:TSMC unveils 1.6nm process technology with backside power... by pjc50 on Friday April 26, 2024 @06:31AM (#40167687)
As someone who worked for a startup that was bought by Cadence: I have some bad news for you about that.
Re:TSMC unveils 1.6nm process technology with backside power... by smj-edison on Thursday April 25, 2024 @09:57PM (#40165153)
Heh, as long as you're not talking about UX...
Re:TSMC unveils 1.6nm process technology with backside power... by fennecbutt on Friday April 26, 2024 @09:49AM (#40169380)
Yeah, I don't think we really have any equivalent technology that is advanced or as detailed as chip making. Chip making is kind of the parent of pretty much every other technology we have at this point.