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A comment on Tenstorrent unveils Grayskull, its RISC-V answer to GPUs. Parent comment

Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by Pet_Ant on Sunday March 10, 2024 @02:52PM (#39661536)
Sounds like a manycore architecture. If you have played TIS-100 it is that exact same idea. If you haven’t, but have played Factorio think of instead of having a central area where all the work happens you build a series of interconnected stations, each doing their own part of calculation before passing it onto the next.

Upside is each core has its own code and is fully Turing complete and independent of eachother. You can handle conditionals much better. And you lose the latency of having network hops for workers.

Downside is you need to break down your process to map onto specific nodes and flows.

(Assuming it is in fact manycore - which is not the same as multicore)

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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by pavlov on Sunday March 10, 2024 @04:16PM (#39662224)
Sounds kind of like the IBM/Sony/Toshiba Cell? It made an appearance in the PlayStation 3, but was supposed to be a more general high-performance architecture. At some point IBM sold blade servers with Cell processors.
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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by amelius on Sunday March 10, 2024 @06:26PM (#39663020)
Is that a dataflow architecture?

https://en.wikipedia.org/wiki/Dataflow_architecture

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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by yvdriess on Sunday March 10, 2024 @07:34PM (#39663390)
No, the Cell is a many-core architecture with a Power 'general' core and 6-8 'special purpose' vector processing units.
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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by marty1885 on Monday March 11, 2024 @05:04AM (#39666005)
Yes. "Coarse-grain dataflow processor". It's like an FPGA. But LUTs are replaced with RISC-V cores.
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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by bschne on Sunday March 10, 2024 @03:10PM (#39661682)
> You can handle conditionals much better

Because you can have a core set up for each branch and just pass to that vs. “context-switching” your core to execute the branch that ends up being taken?

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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by vrighter on Sunday March 10, 2024 @03:19PM (#39661761)
because each core has its own instruction counter
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Re:Tenstorrent unveils Grayskull, its RISC-V answer to GPUs by Pet_Ant on Monday March 11, 2024 @09:44AM (#39668154)
Both

> Because you can have a core set up for each branch

and

> because each core has its own instruction counter

You can have each core be a tighter loop because you can limit the types of cases it handles.

But you also have your own instruction program counter you can take all sorts of branches in a way that you can't with SIMD, because in SIMD as the name implies you get only a Single-Instruction to deal with Multiple-Data. So if you need to change the behaviour depending on the exact value of the data, you are better off using separate cores than wider vectors.

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