More points for someone who wire-wraps a bunch of transistors.

EDIT: This is the one using discrete transistors (http://www.6502.org/users/dieter/mt15/mt15.htm)

(http://www.bigmessowires.com/bmow1/)

(http://web.cecs.pdx.edu/~harry/Relay/index.html)

(http://www.nablaman.com/relay/)

(http://www.northdownfarm.co.uk/rory/tim/)

etc etc

(And see other sites on the homebrew CPU web ring.)

Since there is already two implementations of it in verilog wouldn't it be a relatively simple matter of compiling and loading those unto an FPGA?

Also what is the exchange rate of internet points to HN/reddit karma these days?

I could even say that writing vhdl code for it would be very straightforward, maybe even more so than some of the stuff already made.

There's already a pipelined DCPU-16 Verilog implementation:

http://sybreon.github.com/dcpu16/

Awesome.

I should have known :)