Intel, Samsung, and TSMC Demo 3D-Stacked Transistors

Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors by adgjlsfhk1 on Saturday December 16, 2023 @11:45PM (#38670390)

the caches are already ~75% of the space. you can't significantly increase that. On die ram is also relatively unlikely due to process differences. my best guess is more 3d cache chips. if we can get the interconnects small enough and fast enough, I could see a future where the logic is stacked on top of a dozen (physical) layers of stacked cache

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Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors by iopq on Sunday December 17, 2023 @01:16AM (#38670761)

AMD stacked cache is a significant increase and gives a huge boost in certain gaming scenarios, to the point that it's a 100% increase in certain games that rely on huge caches

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Re:Intel, Samsung, and TSMC Demo 3D-Stacked Transistors by markhahn on Sunday December 17, 2023 @10:56AM (#38673664)

stacking is a heat problem, and heat has been the PRIMARY system limit for over a decade.

2.5d is just too easy and effective - we're going to have lots more chiplets, and only the cool ones will get stacked.

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