A Single-Cycle 64-Bit RISC-V Register File

Re:A Single-Cycle 64-Bit RISC-V Register File by tverbeure on Friday August 04, 2023 @01:21PM (#37002978)

On an FPGA, it will infer a dual-ported BRAM memory just fine. On ASIC, it will generate a flip-flop array, which is good enough for many CPUs.

E.g. in this physical layout of a Swerv RISC-V CPU, the ARF section is the register file, built out of flip-flops: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-ph....

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Re:A Single-Cycle 64-Bit RISC-V Register File by alain94040 on Friday August 04, 2023 @06:03PM (#37006451)

Also, the read ports are asynchronous, which is bad:

    assign rv1 = registers[rs1];
    assign rv2 = registers[rs2];

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