Re:A Single-Cycle 64-Bit RISC-V Register File
by alain94040 on Friday August 04, 2023 @11:36AM
(#37001462)
Correct. The code shown is only good enough for RTL simulation. It won't help actually generate a chip with multiple read and write ports to a register file.
[ Parent
| on HN ]
Re:A Single-Cycle 64-Bit RISC-V Register File
by therealcamino on Friday August 04, 2023 @12:30PM
(#37002256)
That code is synthesizeable and will work fine in an ASIC flow.
Re:A Single-Cycle 64-Bit RISC-V Register File
by tverbeure on Friday August 04, 2023 @01:21PM
(#37002978)
On an FPGA, it will infer a dual-ported BRAM memory just fine. On ASIC, it will generate a flip-flop array, which is good enough for many CPUs.
E.g. in this physical layout of a Swerv RISC-V CPU, the ARF section is the register file, built out of flip-flops: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-ph....
Re:A Single-Cycle 64-Bit RISC-V Register File
by alain94040 on Friday August 04, 2023 @06:03PM
(#37006451)
Also, the read ports are asynchronous, which is bad:
assign rv1 = registers[rs1];
assign rv2 = registers[rs2];