Seems like the latter

Looking more closely at snitch, unfortunately it looks like the two largest contributors have already left the project. Perhaps they can keep momentum but industry poaching remains an issue for ESA.

RISC-V has Vector instruction that do help accelerate many workloads but they are far more general.

Many RISC-V companies have their own AI instructions, there is no standard as this is still a research topic.

There is also no standard for GPU, there is a graphics workgroup as well.

There are currently no chips or boards implementing RVV 1.0. There seems to be a prospect for a board with a single core 1.6 GHz dual-issue in-order core (C908) implementing RVV 1.0 for $30-$40 perhaps towards the end of the year. https://twitter.com/SipeedIO/status/1654055669774036993

There have been chips and boards implementing the mid-2019 RVV draft 0.7.1 since the first Allwinner D1 board with single 1.0 GHz 64 bit C906 core in April 2021 (and a lot more since). In the last few months we have seen three new chips implementing this vector ISA:

- Buffalo Lab BL808 with a 480 MHz C906 (plus a couple of 32 bit cores) and 64 MB of PSRAM: Pine64 Ox64, Sipeed M1s

- THead TH1520 with 4x 2.0 GHz OoO C910 cores similar to Arm A72 in e.g. Pi 4: Lichee Pi 4A, Roma laptop (supposedly), other as yet unannounced boards coming soon

- Sophon SG2042 with 64x 2.0 GHz OoO C910 cores, 64 MB L3 cache, 32x PCIe gen 4, four DDR channels. I've been using one of these remotely via ssh. The first retail machine with it, the Milk-V "Pioneer" is available for preorder in China now, reportedly Crowdsupply soon.

RVV 0.7.1 is very similar to 1.0, but there were a few changes in between that make them incompatible (which is expected because draft specs were never expected to be widely implemented .. but here we are). SOME carefully-written code is binary compatible between them e.g. memcpy(), but in general a little usually trivial conversion is necessary.

I'd rather program directly in assembly language, or in inline asm, than in intrinsics anyway. They are verbose, ugly, hard to write, hard to read, and even hard to modify because things such as the LMUL are baked into every single function name.

I don't know of any document that carefully shows the differences. I'd like to create one, if I had someone to pay for my time to do it.

Here's the source for the compute CPU core: https://github.com/pulp-platform/snitch

At a quick glance, the presentation mentions DMA and local scratchpad memory. Is this similar in approach to the IBM/Sony/Toshiba Cell processor which also had one general purpose core in charge of a fleet of compute-oriented cores?

There's a tremendous usability difference between "X flops and all the different types of cores can read and write to unified memory with cache coherence" (as on Apple Silicon) vs. "X flops but you need to carefully orchestrate chunks of data in and out of local scratchpad buffers" (as on the Cell).

A "Snitch" cluster is 8+1 single-stage small integer cpus +1 DMA core. Cores each have their own "decoupled heavily pipelined" FPU. The cluster shares a L1 I-cache, has 32 banks of 4kB scratchpads, and has a 64bit config / peripheral AXI bus, and a 512bit "wide" AXI bus the +1 DMA core can talk to, and it's own connection to all the scratchpads.

Clusters are grouped together. On this "Occamy" chip, there are 4 Snitch clusters in a group. These groups share the 64bit/512bit AXI group bus, which connects up to top bus. Groups also share a L2 consts cache. Then 6 groups.

The chiplet also has 8 HBM2e chips bringing ~400GBps, and some other goodies, like a 8GBps off-die serial link, a system DMA controller, 8GBps and 64GBps die-to-die serials to connect to other chiplets, and a CVA6 management core.

There's some interesting iterations done to make the FPU more decoupleable, such as having native loop instructions & some interesting memory access instructions with address generation built in- "streaming semantic registers", a neat risc-v isa extension. https://arxiv.org/abs/1911.08356

I love love love the non-cache coherent design. Even within a cluster, there's still not really cache coherence, is my feel; there's just some shared memory one can use. The early slides in this deck so show much promise. Notably, a huge weakness in the ecosystem in general around hard IP for talking to memory, ethernet, PCIe, but otherwise, so much glorious stuff & rapidly improving tools for doing this kind of work.

An AI chip could analyze and compress sensor data locally. It's also could be used for DSP for the communication algorithm.

For comms, that means either more transmission power from a spacecraft that is likely to have been travelling for years, if not decades. Bigger ground or space-based receivers. Or much, much more cost-effectively, reducing bandwidth by adding more bits in error correction. QED using ai to transmit only interesting information becomes attractive.

While for control, it takes between five to twenty minutes for a signal between Earth and Mars, and between Earth and Voyager 1, it's currently twenty-one hours. Adding better control and the ability to cope with more eventualities to a craft that will fly itself in poorly understood situations reduces the cost of trying to achieve a reasonable likelihood of mission success [0].

[0] The alternative being to send one - or more - simpler but still massively expensive craft to determine the missing data ahead of time (and hope it doesn't change).

In the event of an European generalized war with russia, having smaller, nimble data payloads being sent in the downlink is definitely a tactical advantage, as we can certainly expect that one of the first targets of the Russians would be giant, fixed tracking stations.

A surveillance satellite that could interpret images and just send something like "300 tank movement detected in the last hours starting from coordinates X,Y, direction Z, average speed W" in a slow link, able to be received by mobile stations would be great for European defense.

"The chip is being manufactured by Globalfoundries on the 12-nanometer low-power process."

> The chip is being manufactured by Globalfoundries on the 12-nanometer low-power process.

As far as I can tell it is not radiation hardened yet. I think what the article is trying to say is that since it is an open source hardware, ESA is not dependent on the vendor for radiation hardening.

For safety- and mission-critical applications (SC and MC), Verilog is more established in the US, and VHDL is more established in Europe.

For SC, a tool doesn't get any points unless you've used it yourself, so the fact that they occupy the same role and have similar pedigree elsewhere is nearly irrelevant. Each tool permeates all the way down to the less critical roles in order to establish it for more critical use by those specific companies and government agencies. That's how these tools get entrenched in different places.

For MC, you can bring things into your company or agency that are relatively new to your organization or less used in your organization. This processor would at most be used for MC and it's a significant new capability, so it's not all that weird.

The lower the application criticality and the bigger the project impact, the more leeway you can give if there are legitimate project-killing limitations. It's safe to say that the project is impactful because it adds an important sovereign capability, and low criticality because it won't be used for safety and it's not already slated for use in a flagship mission as a mission-killing component.

The only assumption you have to make is why VHDL would be bad. Could be a technical limitation that would be prohibitively expensive to fix. Could be that this group is coming from a non-space background in Verilog and switching to VHDL would be too long and expensive. Or maybe it's a long-term strategic decision to advance the use of Verilog in space because the ESA feels like VHDL will become a liability in the future.

> Ingenuity, also called Ginny, is a small robotic helicopter operating on Mars.

> The helicopter uses a Qualcomm Snapdragon 801 processor

Edit: There is a way to detect and recover from these types of errors. They appear to be able to run the computation on a number of cores with a voter to check for consistency.

Slide 41 (PDF warning): http://microelectronics.esa.int/riscv/rvws2022/presentations...

https://rotorcraft.arc.nasa.gov/Publications/files/Balaram_A...

Also is this chip only really suitable for missions or is this chip also suitable for something like an orbiting datacenter? Or would the earths magnetosphere be able to protect terrestrial chips in orbit from radiation?