Is the source of your core by any chance available online, even if not open sourced?

Not GP, but this might scratch your itch https://github.com/cnlohr/mini-rv32ima

It does, thanks!

It will eventually be in https://github.com/aappleby/Pinwheel but that repo is currently a mess.

That's just what I was wondering about after reading the brief github README:

> The ZPU is a small CPU in two ways: it takes up very little resources and the architecture itself is small.

It would have been nice if they had tried a quantitative comparison with the Risc-V RV32I to support this claim. That would also allow them to showcase the design choices and trade offs that make this project interesting. As it is, there's not much information of this kind to be gained from the README...

> It would have been nice if they had tried a quantitative comparison with the Risc-V RV32I

It would. If they had a Time Machine. ZPU is over a decade and a half old… Back from from when we called RISC-V just "MIPS"

But since you asked. It IS small. The smallest sane RV32 core I can find is PicoRV, which uses 750-2000 LUS[1]. SERV [2] does claim to only need 440 LUTs, but its performance (most instrs take over 32 cycles) makes even ZPU seem speedy... The ZPU uses 442 LUTs[3].

[1] https://github.com/YosysHQ/picorv32

[2] https://github.com/olofk/serv

[3] https://opencores.org/projects/zpu

Note that you can't compare LUT4 results (ZPU @ 440 LUTs) against LUT6 results (PicoRV32 @ 750 LUTs). The ZPU is remarkably small, and it's a bigger gap than a direct comparison shows.

SERV is a fair comparison, since it's architected for 4LUTs and I suspect the synthesis results come from iCE40 tools.

I have a contender in the "very small" space, too [1], although I don't claim it's as mature or complete as SERV. (If Minimax was excluded from your post on the basis of insanity, I'm OK with that.)

[1] https://github.com/gsmecher/minimax

For me the most interesting thing about ZPU is that its instructions are only a single byte each, which means that while the CPU is much smaller than most RISC-V implementations, the code density is significantly better than RV32 code. (Compressed RISC-V code can beat ZPU, but adding the compressed instruction set to a RISC-V core increases its size quite a bit.)

I did play with the ZPU quite a bit 8 or 9 years ago, and forked the ZPU Small variant to create ZPUFlex [0]. I borrowed a number of ideas from ZPU when I created my own CPU Project, EightThirtyTwo [1], some years later.

[0] https://github.com/robinsonb5/ZPUFlex [1] https://github.com/robinsonb5/EightThirtyTwo

The ZPU may be smaller than you're crediting. 440 LUTs is very little space.

The reported synthesis results ("440 LUTs") are on old Spartan-3 fabric. These are LUT4s, and anything from Xilinx newer than about 2006 uses much more capable LUT6s. Hence, it's unfair to compare these figures directly. (Comparing against ICE40 fabric is better.)