iAPX432: Gordon Moore, Risk and Intel’s Super-CISC Failure

Re:iAPX432: Gordon Moore, Risk and Intel’s Super-CISC Failure by flohofwoe on Monday April 03, 2023 @05:33AM (#35420750)

AFAIK there's a 'bit-addressable' extension for ARM, but I lack the google-fu to search for it.

If you go with the (high-level) idea that bytes are nothing special anymore (because cache line width is the new 'word width'), and instead you have arbitrary width integers (like Zig for instance), it would also make sense to have 'bit granularity pointers'.

All you'd need is to move a regular pointer 3 bits to the left (which should be ok because the upper bits are wasted anyway).

IMHO this would make a lot of sense from a system programming language PoV, but I guess the hardware guys can think of a couple of reasons to object :)

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Re:iAPX432: Gordon Moore, Risk and Intel’s Super-CISC Failure by rep_lodsb on Monday April 03, 2023 @10:15AM (#35423943)

Bit-addressable data has been done in at least one other architecture: https://en.wikipedia.org/wiki/TMS34010

This is different from the 432 having opcodes that weren't a multiple of 8 bits, making decoding even more complicated than on x86.

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Re:iAPX432: Gordon Moore, Risk and Intel’s Super-CISC Failure by kjs3 on Monday April 03, 2023 @11:39AM (#35425616)

The Intel 8051 can do limited bit level addressing. It's restricted to a specific 16-byte region in low memory, which it makes it different than either the 432 or 34010.

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