Branch prediction is pretty fundamental to CPU performance; unless we want much slower CPUs it’s necessary.

Although it’s interesting to think about how software could help with branch prediction, the simple answer about the kernel thing is that software is the wrong place in the architecture for branch prediction to happen. Maybe there’s some crazy alternative way things could be done, but in anything like the current computing model branch prediction has to happen in hardware.

> Maybe there’s some crazy alternative way things could be done

"Branchless programming" is an umbrella term for techniques in existing programming languages to avoid branches.

It almost always doesn’t work; if a branch can eliminate a single uncached memory read you’d want to keep that branch.

It’s mostly used for things like min/max operations in cases when you don’t have cmov. Or bitwise SIMD programming.

    CPU Single Thread Rating

    Name                                pts     Date
    Intel Core2 Duo E7600 @ 3.06GHz   1,270     Q2 2009
    Intel Core Solo T1350 @ 1.86GHz     413     Q1 2009
    Intel Core Solo U1300 @ 1.06GHz     340     Q3 2009
    Intel Atom D425 @ 1.80GHz           320     Q1 2011

These Atoms were quite gutted to have a low die size and low TDP, and the first things what were cut are cache and branch prediction. You can see how D425 from 2011 is on the same level as two year earlier and a almost a half GHz slower U1300.

> In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs.[3] This enables relatively good performance with only two integer ALUs, and without any instruction reordering, speculative execution or register renaming. A side effect of having no speculative execution is invulnerability against Meltdown and Spectre.

https://www.cpubenchmark.net/compare/948vs579vs593vs609/Inte...

https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)

Bonnell has a branch predictor: https://en.wikichip.org/wiki/intel/microarchitectures/bonnel...

In-order execution does not mean that there is no branch prediction, it just means that the number of instructions speculated is much smaller.

Yes, it would be quite strange not to add it at all, especially since it was available since Pentium days.

No, it is not comparable with a 'proper' CPUs because it was still gutted hard.

IMMSMV all that stuff consumes a lot of die space, so it makes sense to throw it out if the performance is enough.