Re:IEDM 2022: Did We Just Witness the Death of SRAM?
by Palomides on Wednesday December 14, 2022 @08:40PM
(#33993879)
later Xeon Phi chips had this, 16GB of on-package RAM with 4x the bandwidth of the external RAM
Re:IEDM 2022: Did We Just Witness the Death of SRAM?
by fulafel on Thursday December 15, 2022 @01:44AM
(#33996121)
IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...
(They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)
Re:IEDM 2022: Did We Just Witness the Death of SRAM?
by legulere on Thursday December 15, 2022 @01:09AM
(#33995896)
There’s potentially even more layers. Compute express link allows to expand the system with even more RAM slowly through PCIe
And already now you have NUMA where performance is different and depending on which core you are.
Re:IEDM 2022: Did We Just Witness the Death of SRAM?
by Vogtinator on Thursday December 15, 2022 @03:18AM
(#33996646)
IBM are the masters of this: https://www.anandtech.com/show/16924/did-ibm-just-preview-th...
Processors can use the L2 cache from other (remote) processors before reaching out to DRAM.
Re:IEDM 2022: Did We Just Witness the Death of SRAM?
by Tuna-Fish on Thursday December 15, 2022 @06:55AM
(#33998164)
It adds latency. You have to probe all the earlier levels of the cache before you can access the next one, if you want the caches to help with bandwidth. The cost of probing more levels adds up.
For example, with the M1, Apple tied the DRAM interface to the CPU. That got them more bandwidth, but then you can't upgrade the memory, which is weak.
But why not do both?
Have e.g. 8GB of high-bandwidth DRAM soldered to the board, essentially that amount of L4 cache, but keep the DIMM slots where you can add arbitrarily more memory with less bandwidth.