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Re:IEDM 2022: Did We Just Witness the Death of SRAM? by fulafel on Thursday December 15, 2022 @01:44AM (#33996121)
IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edr...

(They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)

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