What RISC took advantage of was decoupling the memory bus from the CPU clock rate and the introduction of instruction and data caches.
RISC is a simple interface, but the internal processor complexity is as high or higher than CISC (thanks to RISC simplicity). Speculative execution, reordering instructions, hazards, branch prediction these issues are the same across both.
The front end isn't this huge deal. CPUs all do the same thing, attempt to unroll huge state machines and compress time. The ISA is just a way to get that problem into the CPU.
I actually cited an example of a major CISC design that basically failed because it was so buggy.
The early microprocessors all had hard coded microcode - Intel only had upgradeable microcode with P6 in the mid 1990s.
I didn't say that it was the reason - there were many reasons - but that it was one factor. It was absolutely the case that original RISC designs were simpler to design and that helped them to get traction.
1990? No system without soft microcode? That's a very restricted definition of system for the field of computing in 1990.
Intel 8086 was introduced in 1978, with hardcoded microcode. Intel didn’t introduce microcode patching support until the Pentium Pro in 1995.
1. As microprocessors became dominant freezing complex microcode - with possible bugs - on an IC was a really bad idea. Better to run with simpler instructions and less microcode.
Look at the debugging issues that National Semiconductor had with the NS32016 - which I think really hindered its adoption.
2. You needed a much smaller team to design a RISC CPU - low double figures for IBM 801, Berkeley RISC, MIPS and Arm. This opened the door to lots of experiments and business models that would not have been possible with CISC.