Re:RISC in 2022
by klelatti on Saturday October 22, 2022 @03:15PM
(#33301234)
The key word in my comment is ‘early’. You’re right about architectures today but that explicitly wasn’t what I was talking about. Caches we’re important in the IBM 801 but your orher points don’t apply to early RISC designs.
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RISC didn't hit its stride until the early 80s, using caches. The 801 was an experiment. When the 801 shipped, almost no system had hard coded microcode. Being able to update microcode in the field isn't the reason RISC thrived.
I can think of at least two of the RISC pioneers who have cited buggy CISC architectures / microcode as a key motivating reason for adopting RISC.
I actually cited an example of a major CISC design that basically failed because it was so buggy.
The early microprocessors all had hard coded microcode - Intel only had upgradeable microcode with P6 in the mid 1990s.
I didn't say that it was the reason - there were many reasons - but that it was one factor. It was absolutely the case that original RISC designs were simpler to design and that helped them to get traction.
> When the 801 shipped, almost no system had hard coded microcode.
1990? No system without soft microcode? That's a very restricted definition of system for the field of computing in 1990.
> When the 801 shipped, almost no system had hard coded microcode.
Intel 8086 was introduced in 1978, with hardcoded microcode. Intel didn’t introduce microcode patching support until the Pentium Pro in 1995.