RISC-V is getting MSIs

Re:RISC-V is getting MSIs by amelius on Thursday June 30, 2022 @03:31PM (#31937378)

What is the max latency of these signals?

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Re:RISC-V is getting MSIs by monocasa on Thursday June 30, 2022 @03:41PM (#31937545)

Depends on the system architecture. But a lot of complex systems have been message signaled internally for a very long time, hypertransport based systems being a prominent early example in the desktop/server space.

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Re:RISC-V is getting MSIs by eqvinox on Thursday June 30, 2022 @04:39PM (#31938295)

Indeed there are no interrupt pins in PCI express at all, you only have a choice between special "Legacy/Compatibility" Assert_INTx message packets, or plain Memory Writes for MSI/MSI-X. But both are carried as in-band PCIe packets on the high speed lanes.

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