RISC-V doesn't have hardware mul/div in it's baseline spec. There's a "Zmmul" extension that adds mul, and the full "M" extension which includes mul/div. Technically, those extensions are optional, but I think most current hardware implementations include them.

That's...very weird I guess? Hardware mul/div requires so little chip real-estate relative to the whole die these days, and has such obvious advantage, why did they make it optional?

The point of the baseline spec, as far as I know, is to make a modern chip design that even the smallest fab or ASIC can build on its own.

I wrote almost nothing but assembly for ten years (mid 80s to mid 90s) and I think I can count on one hand the number of times I actually needed a generalized multiplication/division instruction. Heck, even square root could be done with repeated subtraction which could be Good Enough(TM), or maybe a lookup table.

The SeRV implementation of RISC-V fits into 200 4-LUTs on an ICE40 FPGA. If your FPGA doesn't have a multiplier, how many 4-LUTs do you need to build a 32x32 multiplier? I'm guessing the answer is comparable to 200.

Ah, you're right. I'm thinking in terms of transistors, not LUTs.

I think the case is even stronger if you're counting in transistors, because FPGAs usually come with multipliers built in, but bare silicon wafers don't. A CPU such as a 6502 or an Intersil 6100 (a PDP-8 on a chip) costs on the order of 4000 transistors. I suspect SeRV would be about the same size, maybe a bit smaller. How many transistors do you need for a 32-bit multiplier?

IIUC this is because:

* mul/div take a lot of transistors and may not be a single or fixed cycle instruction.

* A lot of embedded systems don't really need those instructions anyway - they just encode discrete state machines or do something like networking that doesn't need * or / for operation.

* less transistors means the chips are cheaper, and single (or fixed) cycles per instruction means hard real-time is simpler to reason about.

Is that correct?