Multiplying and Dividing on the 6502 (2021)

Re:Multiplying and Dividing on the 6502 (2021) by kragen on Tuesday June 28, 2022 @08:32PM (#31914993)

The SeRV implementation of RISC-V fits into 200 4-LUTs on an ICE40 FPGA. If your FPGA doesn't have a multiplier, how many 4-LUTs do you need to build a 32x32 multiplier? I'm guessing the answer is comparable to 200.

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Re:Multiplying and Dividing on the 6502 (2021) by kjs3 on Tuesday June 28, 2022 @11:35PM (#31916180)

Ah, you're right. I'm thinking in terms of transistors, not LUTs.

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Re:Multiplying and Dividing on the 6502 (2021) by kragen on Wednesday June 29, 2022 @12:33AM (#31916540)

I think the case is even stronger if you're counting in transistors, because FPGAs usually come with multipliers built in, but bare silicon wafers don't. A CPU such as a 6502 or an Intersil 6100 (a PDP-8 on a chip) costs on the order of 4000 transistors. I suspect SeRV would be about the same size, maybe a bit smaller. How many transistors do you need for a 32-bit multiplier?

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