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Re:MIPS provides highly scalable RISC processor IP by zozbot234 on Thursday April 07, 2022 @07:20AM (#30943036)
A fixed zero register is a trivial "increase in the number of registers". To be fair there's very little real-world code that even comes close to making use of 16 registers, let alone 32. So if you really wanted to optimize use of the encoding space, that would be something to focus on first.
Re:MIPS provides highly scalable RISC processor IP by gpderetta on Thursday April 07, 2022 @08:51AM (#30943756)
sorry for the confusion, by "increase the number of registers" I meant the arity of an instruction (3 for risc vs the typical 2 for x86). So you need an additional log2 bits to encode the extra operand.