Re:MIPS provides highly scalable RISC processor IP
by zozbot234 on Thursday April 07, 2022 @07:20AM
(#30943036)
A fixed zero register is a trivial "increase in the number of registers". To be fair there's very little real-world code that even comes close to making use of 16 registers, let alone 32. So if you really wanted to optimize use of the encoding space, that would be something to focus on first.
Re:MIPS provides highly scalable RISC processor IP
by gpderetta on Thursday April 07, 2022 @08:51AM
(#30943756)
sorry for the confusion, by "increase the number of registers" I meant the arity of an instruction (3 for risc vs the typical 2 for x86). So you need an additional log2 bits to encode the extra operand.
but the same advanced implementation that can break dependencies when reading/writing to r0 can do the same when handling xor r0,r0. Indeed that's exactly what many CPUs do.
I'm not qualified to say whether a zero register is better or not, but I will mention that it basically requires your ISA to be 3 operands that has a cost in term of instruction length: so you save bits to have a smaller set of instructions, but need more bits to increase the number of registers.
RISCs are usually 3 operands anyway for many reasons, so in practice it doesn't make a difference I guess.