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A comment on Verilog Is Weird. Parent comment

Re:Verilog Is Weird by buildbot on Wednesday March 23, 2022 @10:39AM (#30778901)
This is not exactly true, because the event you expect in software, the loop ticking over, can itself happen at any time. posedge(*) will trigger on _any_ change in the always block, and those changes can happen at the same, slightly different, or much different times.
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Re:Verilog Is Weird by tails4e on Sunday March 27, 2022 @08:01AM (#30819591)
always( * ) is not the same as always, I was referring to the latter. always( * ) is gated by the sensitivity list, always is not.
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