Verilog Is Weird

Re:Verilog Is Weird by tails4e on Wednesday March 23, 2022 @07:50AM (#30777483)

I think the loop term is OK, it's just gated by the event sensitivity list for each iteration. If you have an always without a sensitivity list then it is a while(1) equivalent.

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Re:Verilog Is Weird by buildbot on Wednesday March 23, 2022 @10:39AM (#30778901)

This is not exactly true, because the event you expect in software, the loop ticking over, can itself happen at any time. posedge(*) will trigger on _any_ change in the always block, and those changes can happen at the same, slightly different, or much different times.

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Re:Verilog Is Weird by tails4e on Sunday March 27, 2022 @08:01AM (#30819591)

always( * ) is not the same as always, I was referring to the latter. always( * ) is gated by the sensitivity list, always is not.

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